Tim Edwards e6a94449ce Modified the housekeeping SPI to generate a read strobe (or rather ... status) so that between rdstb and wrstb, the SPI signals when it is about to read or write a byte. The back-door wishbone interface then stalls the CPU during these periods. That allows the CPU to continue running while the SPI is being accessed without data collisions and without having to stall for the entire time CSB is held low. Because SCK is asynchronous to the clock, rare collisions are still possible; this is not expected to be an issue but might be worth investigating.		2021-10-23 22:06:24 -04:00
..
__uprj_analog_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__uprj_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan_netlists.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
caravel.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
caravel_clocking.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel_netlists.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
caravel_openframe.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io_alt.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
clock_div.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
defines.v	Correction to the mprj_bitbang testbench to run the test without running	2021-10-21 10:57:20 -04:00
digital_pll.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
digital_pll_controller.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_control_block.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
gpio_defaults_block.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
gpio_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
housekeeping.v	Modified the housekeeping SPI to generate a read strobe (or rather	2021-10-23 22:06:24 -04:00
housekeeping_spi.v	Modified the housekeeping SPI to generate a read strobe (or rather	2021-10-23 22:06:24 -04:00
mgmt_protect.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mgmt_protect_hv.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj2_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
pads.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
ring_osc2x13.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
simple_por.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
user_defines.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
user_id_programming.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00