status) so that between rdstb and wrstb, the SPI signals when it is
about to read or write a byte. The back-door wishbone interface then
stalls the CPU during these periods. That allows the CPU to continue
running while the SPI is being accessed without data collisions and
without having to stall for the entire time CSB is held low.
Because SCK is asynchronous to the clock, rare collisions are still
possible; this is not expected to be an issue but might be worth
investigating.
via programming. The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file. For the verilog, they are
applied as parameters. For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master. Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
storage. Not all of these pass simulation checks. Added back the
bit-bang control of the GPIO programming. Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports. There is not yet a testbench for the SRAM read-only
interface.
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262... Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
Tim Edwards