mirror of https://github.com/efabless/caravel.git
65 lines
2.9 KiB
Tcl
65 lines
2.9 KiB
Tcl
## MASTER CLOCKS
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create_clock [get_ports {"ext_clk"} ] -name "ext_clk" -period 25
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create_clock [get_ports {"pll_clk"} ] -name "pll_clk" -period 6.6666666666667
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create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90" -period 6.6666666666667
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set muxes_2 [list $::env(STD_CELL_LIBRARY)__mux2_1 $::env(STD_CELL_LIBRARY)__mux2_2 $::env(STD_CELL_LIBRARY)__mux2_4 $::env(STD_CELL_LIBRARY)__mux2_8]
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foreach mux_2 $muxes_2 {
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set mux2_instance [get_cells -of_objects core_clk -filter ref_name==$mux_2]
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if { $mux2_instance ne "" } {
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puts "\[caravel_clocking_sdc\] found mux2: $mux2_instance"
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break
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}
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}
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set core_clk_pin [get_pins -filter lib_pin_name==X -of_objects $mux2_instance]
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## GENERATED CLOCKS
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create_generated_clock -name core_clk -source $core_clk_pin -divide_by 1 [get_ports core_clk]
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# logically exclusive clocks, the generated pll clocks and the ext core clk
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set_clock_groups -logically_exclusive -group ext_clk -group {pll_clk90 pll_clk}
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## INPUT/OUTPUT DELAYS
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set ext_clk_input_delay_value 5
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set ext_clk_output_delay_value 5
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
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#set_input_delay $input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
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set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
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set_output_delay $ext_clk_output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
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# TODO set this as parameter
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set cap_load 0.2
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set_load $cap_load [all_outputs]
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set_timing_derate -early 0.9500
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set_timing_derate -late 1.0500
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set_clock_uncertainty 0.2 [get_clocks {ext_clk}]
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set_clock_uncertainty 0.2 [get_clocks {pll_clk}]
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set_clock_uncertainty 0.2 [get_clocks {pll_clk90}]
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set_clock_uncertainty 0.2 [get_clocks {core_clk}]
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set_clock_transition 0.15 [get_clocks {ext_clk}]
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set_clock_transition 0.1 [get_clocks {pll_clk}]
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set_clock_transition 0.1 [get_clocks {pll_clk90}]
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set_clock_transition 0.1 [get_clocks {core_clk}]
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set_max_transition 0.5 [all_clocks] -clock_path
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#set clk_input [get_port serial_clock)]
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#set clk_indx [lsearch [all_inputs] $clk_input]
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#set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
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set_input_transition 5.0 [all_inputs]
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set_max_transition 0.75 [current_design]
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