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.github/workflows
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Update auto-update-caravel-lite.yml
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2021-12-15 23:38:04 -08:00 |
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def
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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doc
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Updated the floorplan.
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2021-11-10 12:21:22 -05:00 |
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gds
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[DATA] Update chip_io_alt.gds to match the mag view
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2021-12-09 22:15:05 +02:00 |
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lef
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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mag
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Corrected a typo in the run_chip_io_alt_lvs.sh script.
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2021-12-08 10:06:50 -05:00 |
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maglef
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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openlane
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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scripts
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Correction to the gen_gpio_defaults.py file, which was accidentally
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2021-12-04 12:41:06 -05:00 |
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sdc
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Update sdf file divider
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2021-12-14 14:30:00 +02:00 |
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sdf
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Update sdf file divider
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2021-12-14 14:30:00 +02:00 |
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signoff
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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spef
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Update sdf file divider
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2021-12-14 14:30:00 +02:00 |
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spi/lvs
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[DATA] Update caravel_clocking
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2021-12-07 13:36:56 +02:00 |
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verilog
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Modified simple_por.v RTL to avoid the wire declaration that "cvc"
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2021-12-08 12:16:19 -05:00 |
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xschem
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Added the files for the simple_por block design, and placed the latest
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2021-11-15 10:34:52 -05:00 |
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.gitignore
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added install_mcw make target
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2021-11-24 09:23:58 -08:00 |
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LICENSE
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Create LICENSE
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2021-12-15 23:53:39 -08:00 |
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Makefile
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Update sdf file divider
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2021-12-14 14:30:00 +02:00 |
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README.md
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Update README.md
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2021-10-12 10:28:29 -07:00 |
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