caravel/signoff/caravel_core/metrics.csv

1	Metric	Value
2	design__instance__count	46948
3	design__instance__area	12589400
4	design__instance_unmapped__count	0
5	synthesis__check_error__count	0
6	design__die__bbox	0.0 0.0 3165.0 4767.0
7	design__core__bbox	10.12 10.88 3154.68 4754.56
8	design__io	633
9	design__die__area	15087600
10	design__core__area	14916800
11	design__instance__count__stdcell	46854
12	design__instance__area__stdcell	140192
13	design__instance__count__macros	94
14	design__instance__area__macros	12449200
15	design__instance__utilization	0.843975
16	design__instance__utilization__stdcell	0.0568134
17	design__power_grid_violation__count__net:vccd1	8
18	design__power_grid_violation__count__net:vssd1	10
19	design__power_grid_violation__count__net:vssio	127
20	design__power_grid_violation__count__net:vccd	53152
21	design__power_grid_violation__count__net:vdda1	804
22	design__power_grid_violation__count__net:vssa2	870
23	design__power_grid_violation__count__net:vssd2	800
24	design__power_grid_violation__count__net:vdda2	804
25	design__power_grid_violation__count__net:vddio	127
26	design__power_grid_violation__count__net:vssd	1249
27	design__power_grid_violation__count__net:vccd2	804
28	design__power_grid_violation__count__net:vssa1	828
29	design__power_grid_violation__count	59583
30	timing__drv__floating__nets	34
31	timing__drv__floating__pins	0
32	design__instance__displacement__total	0
33	design__instance__displacement__mean	0
34	design__instance__displacement__max	0
35	route__wirelength__estimated	1617310
36	design__violations	0
37	design__instance__count__setup_buffer	0
38	design__instance__count__hold_buffer	0
39	antenna__violating__nets	107
40	antenna__violating__pins	107
41	route__antenna_violation__count	107
42	route__net	7907
43	route__net__special	12
44	route__drc_errors__iter:1	9881
45	route__wirelength__iter:1	1671546
46	route__drc_errors__iter:2	3615
47	route__wirelength__iter:2	1670366
48	route__drc_errors__iter:3	3129
49	route__wirelength__iter:3	1669922
50	route__drc_errors__iter:4	848
51	route__wirelength__iter:4	1671982
52	route__drc_errors__iter:5	406
53	route__wirelength__iter:5	1671982
54	route__drc_errors__iter:6	311
55	route__wirelength__iter:6	1672038
56	route__drc_errors__iter:7	266
57	route__wirelength__iter:7	1672027
58	route__drc_errors__iter:8	192
59	route__wirelength__iter:8	1672267
60	route__drc_errors__iter:9	96
61	route__wirelength__iter:9	1672170
62	route__drc_errors__iter:10	69
63	route__wirelength__iter:10	1672235
64	route__drc_errors__iter:11	1
65	route__wirelength__iter:11	1672299
66	route__drc_errors__iter:12	1
67	route__wirelength__iter:12	1672302
68	route__drc_errors__iter:13	0
69	route__wirelength__iter:13	1672308
70	route__drc_errors	0
71	route__wirelength	1672308
72	route__vias	62823
73	route__vias__singlecut	62823
74	route__vias__multicut	0
75	design__disconnected_pin__count	4
76	design__critical_disconnected_pin__count	0
77	route__wirelength__max	4055.92
78	design__max_slew_violation__count__corner:nom_tt_025C_1v80	88
79	design__max_fanout_violation__count__corner:nom_tt_025C_1v80	2732
80	design__max_cap_violation__count__corner:nom_tt_025C_1v80	27
81	power__internal__total	0.005174397025257349
82	power__switching__total	0.009033364243805408
83	power__leakage__total	0.0000018623289861352532
84	power__total	0.014209624379873276
85	clock__skew__worst_hold__corner:nom_tt_025C_1v80	7.544759
86	clock__skew__worst_setup__corner:nom_tt_025C_1v80	8.099279
87	timing__hold__ws__corner:nom_tt_025C_1v80	0.24937
88	timing__setup__ws__corner:nom_tt_025C_1v80	4.266059
89	timing__hold__tns__corner:nom_tt_025C_1v80	0.0
90	timing__setup__tns__corner:nom_tt_025C_1v80	0.0
91	timing__hold__wns__corner:nom_tt_025C_1v80	0.0
92	timing__setup__wns__corner:nom_tt_025C_1v80	0.0
93	timing__hold_vio__count__corner:nom_tt_025C_1v80	0
94	timing__hold_r2r__ws__corner:nom_tt_025C_1v80	0.24937
95	timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80	0
96	timing__setup_vio__count__corner:nom_tt_025C_1v80	0
97	timing__setup_r2r__ws__corner:nom_tt_025C_1v80	6.117834
98	timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80	0
99	timing__unannotated_net__count__corner:nom_tt_025C_1v80	1413
100	timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80	0
101	design__max_slew_violation__count__corner:nom_ss_100C_1v60	686
102	design__max_fanout_violation__count__corner:nom_ss_100C_1v60	2732
103	design__max_cap_violation__count__corner:nom_ss_100C_1v60	578
104	clock__skew__worst_hold__corner:nom_ss_100C_1v60	10.131796
105	clock__skew__worst_setup__corner:nom_ss_100C_1v60	11.207791
106	timing__hold__ws__corner:nom_ss_100C_1v60	0.490234
107	timing__setup__ws__corner:nom_ss_100C_1v60	0.477664
108	timing__hold__tns__corner:nom_ss_100C_1v60	0.0
109	timing__setup__tns__corner:nom_ss_100C_1v60	0.0
110	timing__hold__wns__corner:nom_ss_100C_1v60	0.0
111	timing__setup__wns__corner:nom_ss_100C_1v60	0.0
112	timing__hold_vio__count__corner:nom_ss_100C_1v60	0
113	timing__hold_r2r__ws__corner:nom_ss_100C_1v60	0.666247
114	timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60	0
115	timing__setup_vio__count__corner:nom_ss_100C_1v60	0
116	timing__setup_r2r__ws__corner:nom_ss_100C_1v60	0.477664
117	timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60	0
118	timing__unannotated_net__count__corner:nom_ss_100C_1v60	1413
119	timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60	0
120	design__max_slew_violation__count__corner:nom_ff_n40C_1v95	88
121	design__max_fanout_violation__count__corner:nom_ff_n40C_1v95	2732
122	design__max_cap_violation__count__corner:nom_ff_n40C_1v95	27
123	clock__skew__worst_hold__corner:nom_ff_n40C_1v95	6.409457
124	clock__skew__worst_setup__corner:nom_ff_n40C_1v95	6.716522
125	timing__hold__ws__corner:nom_ff_n40C_1v95	0.115054
126	timing__setup__ws__corner:nom_ff_n40C_1v95	5.555556
127	timing__hold__tns__corner:nom_ff_n40C_1v95	0.0
128	timing__setup__tns__corner:nom_ff_n40C_1v95	0.0
129	timing__hold__wns__corner:nom_ff_n40C_1v95	0.0
130	timing__setup__wns__corner:nom_ff_n40C_1v95	0.0
131	timing__hold_vio__count__corner:nom_ff_n40C_1v95	0
132	timing__hold_r2r__ws__corner:nom_ff_n40C_1v95	0.115054
133	timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95	0
134	timing__setup_vio__count__corner:nom_ff_n40C_1v95	0
135	timing__setup_r2r__ws__corner:nom_ff_n40C_1v95	8.421376
136	timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95	0
137	timing__unannotated_net__count__corner:nom_ff_n40C_1v95	1413
138	timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95	0
139	design__max_slew_violation__count__corner:min_tt_025C_1v80	16
140	design__max_fanout_violation__count__corner:min_tt_025C_1v80	2732
141	design__max_cap_violation__count__corner:min_tt_025C_1v80	4
142	clock__skew__worst_hold__corner:min_tt_025C_1v80	7.366073
143	clock__skew__worst_setup__corner:min_tt_025C_1v80	7.892606
144	timing__hold__ws__corner:min_tt_025C_1v80	0.25943
145	timing__setup__ws__corner:min_tt_025C_1v80	4.518233
146	timing__hold__tns__corner:min_tt_025C_1v80	0.0
147	timing__setup__tns__corner:min_tt_025C_1v80	0.0
148	timing__hold__wns__corner:min_tt_025C_1v80	0.0
149	timing__setup__wns__corner:min_tt_025C_1v80	0.0
150	timing__hold_vio__count__corner:min_tt_025C_1v80	0
151	timing__hold_r2r__ws__corner:min_tt_025C_1v80	0.25943
152	timing__hold_r2r_vio__count__corner:min_tt_025C_1v80	0
153	timing__setup_vio__count__corner:min_tt_025C_1v80	0
154	timing__setup_r2r__ws__corner:min_tt_025C_1v80	6.463109
155	timing__setup_r2r_vio__count__corner:min_tt_025C_1v80	0
156	timing__unannotated_net__count__corner:min_tt_025C_1v80	1413
157	timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80	0
158	design__max_slew_violation__count__corner:min_ss_100C_1v60	39
159	design__max_fanout_violation__count__corner:min_ss_100C_1v60	2732
160	design__max_cap_violation__count__corner:min_ss_100C_1v60	91
161	clock__skew__worst_hold__corner:min_ss_100C_1v60	9.851759
162	clock__skew__worst_setup__corner:min_ss_100C_1v60	10.882171
163	timing__hold__ws__corner:min_ss_100C_1v60	0.641937
164	timing__setup__ws__corner:min_ss_100C_1v60	1.114103
165	timing__hold__tns__corner:min_ss_100C_1v60	0.0
166	timing__setup__tns__corner:min_ss_100C_1v60	0.0
167	timing__hold__wns__corner:min_ss_100C_1v60	0.0
168	timing__setup__wns__corner:min_ss_100C_1v60	0.0
169	timing__hold_vio__count__corner:min_ss_100C_1v60	0
170	timing__hold_r2r__ws__corner:min_ss_100C_1v60	0.663174
171	timing__hold_r2r_vio__count__corner:min_ss_100C_1v60	0
172	timing__setup_vio__count__corner:min_ss_100C_1v60	0
173	timing__setup_r2r__ws__corner:min_ss_100C_1v60	1.114103
174	timing__setup_r2r_vio__count__corner:min_ss_100C_1v60	0
175	timing__unannotated_net__count__corner:min_ss_100C_1v60	1413
176	timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60	0
177	design__max_slew_violation__count__corner:min_ff_n40C_1v95	16
178	design__max_fanout_violation__count__corner:min_ff_n40C_1v95	2732
179	design__max_cap_violation__count__corner:min_ff_n40C_1v95	4
180	clock__skew__worst_hold__corner:min_ff_n40C_1v95	6.278924
181	clock__skew__worst_setup__corner:min_ff_n40C_1v95	6.565427
182	timing__hold__ws__corner:min_ff_n40C_1v95	0.122159
183	timing__setup__ws__corner:min_ff_n40C_1v95	5.775887
184	timing__hold__tns__corner:min_ff_n40C_1v95	0.0
185	timing__setup__tns__corner:min_ff_n40C_1v95	0.0
186	timing__hold__wns__corner:min_ff_n40C_1v95	0.0
187	timing__setup__wns__corner:min_ff_n40C_1v95	0.0
188	timing__hold_vio__count__corner:min_ff_n40C_1v95	0
189	timing__hold_r2r__ws__corner:min_ff_n40C_1v95	0.122159
190	timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95	0
191	timing__setup_vio__count__corner:min_ff_n40C_1v95	0
192	timing__setup_r2r__ws__corner:min_ff_n40C_1v95	8.628211
193	timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95	0
194	timing__unannotated_net__count__corner:min_ff_n40C_1v95	1413
195	timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95	0
196	design__max_slew_violation__count__corner:max_tt_025C_1v80	111
197	design__max_fanout_violation__count__corner:max_tt_025C_1v80	2732
198	design__max_cap_violation__count__corner:max_tt_025C_1v80	32
199	clock__skew__worst_hold__corner:max_tt_025C_1v80	7.71846
200	clock__skew__worst_setup__corner:max_tt_025C_1v80	8.301414
201	timing__hold__ws__corner:max_tt_025C_1v80	0.235833
202	timing__setup__ws__corner:max_tt_025C_1v80	3.997819
203	timing__hold__tns__corner:max_tt_025C_1v80	0.0
204	timing__setup__tns__corner:max_tt_025C_1v80	0.0
205	timing__hold__wns__corner:max_tt_025C_1v80	0.0
206	timing__setup__wns__corner:max_tt_025C_1v80	0.0
207	timing__hold_vio__count__corner:max_tt_025C_1v80	0
208	timing__hold_r2r__ws__corner:max_tt_025C_1v80	0.235833
209	timing__hold_r2r_vio__count__corner:max_tt_025C_1v80	0
210	timing__setup_vio__count__corner:max_tt_025C_1v80	0
211	timing__setup_r2r__ws__corner:max_tt_025C_1v80	5.915514
212	timing__setup_r2r_vio__count__corner:max_tt_025C_1v80	0
213	timing__unannotated_net__count__corner:max_tt_025C_1v80	1413
214	timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80	0
215	design__max_slew_violation__count__corner:max_ss_100C_1v60	1705
216	design__max_fanout_violation__count__corner:max_ss_100C_1v60	2732
217	design__max_cap_violation__count__corner:max_ss_100C_1v60	1435
218	clock__skew__worst_hold__corner:max_ss_100C_1v60	10.385975
219	clock__skew__worst_setup__corner:max_ss_100C_1v60	11.50234
220	timing__hold__ws__corner:max_ss_100C_1v60	0.373463
221	timing__setup__ws__corner:max_ss_100C_1v60	0.073893
222	timing__hold__tns__corner:max_ss_100C_1v60	0.0
223	timing__setup__tns__corner:max_ss_100C_1v60	0.0
224	timing__hold__wns__corner:max_ss_100C_1v60	0.0
225	timing__setup__wns__corner:max_ss_100C_1v60	0.0
226	timing__hold_vio__count__corner:max_ss_100C_1v60	0
227	timing__hold_r2r__ws__corner:max_ss_100C_1v60	0.670588
228	timing__hold_r2r_vio__count__corner:max_ss_100C_1v60	0
229	timing__setup_vio__count__corner:max_ss_100C_1v60	0
230	timing__setup_r2r__ws__corner:max_ss_100C_1v60	0.073893
231	timing__setup_r2r_vio__count__corner:max_ss_100C_1v60	0
232	timing__unannotated_net__count__corner:max_ss_100C_1v60	1413
233	timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60	0
234	design__max_slew_violation__count__corner:max_ff_n40C_1v95	111
235	design__max_fanout_violation__count__corner:max_ff_n40C_1v95	2732
236	design__max_cap_violation__count__corner:max_ff_n40C_1v95	32
237	clock__skew__worst_hold__corner:max_ff_n40C_1v95	6.533941
238	clock__skew__worst_setup__corner:max_ff_n40C_1v95	6.861891
239	timing__hold__ws__corner:max_ff_n40C_1v95	0.102694
240	timing__setup__ws__corner:max_ff_n40C_1v95	5.30355
241	timing__hold__tns__corner:max_ff_n40C_1v95	0.0
242	timing__setup__tns__corner:max_ff_n40C_1v95	0.0
243	timing__hold__wns__corner:max_ff_n40C_1v95	0.0
244	timing__setup__wns__corner:max_ff_n40C_1v95	0.0
245	timing__hold_vio__count__corner:max_ff_n40C_1v95	0
246	timing__hold_r2r__ws__corner:max_ff_n40C_1v95	0.102694
247	timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95	0
248	timing__setup_vio__count__corner:max_ff_n40C_1v95	0
249	timing__setup_r2r__ws__corner:max_ff_n40C_1v95	8.293603
250	timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95	0
251	timing__unannotated_net__count__corner:max_ff_n40C_1v95	1413
252	timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95	0
253	design__max_slew_violation__count	1705
254	design__max_fanout_violation__count	2732
255	design__max_cap_violation__count	1435
256	clock__skew__worst_hold	10.385975
257	clock__skew__worst_setup	6.565427
258	timing__hold__ws	0.102694
259	timing__setup__ws	0.073893
260	timing__hold__tns	0.0
261	timing__setup__tns	0.0
262	timing__hold__wns	0.0
263	timing__setup__wns	0.0
264	timing__hold_vio__count	0
265	timing__hold_r2r__ws	0.102694
266	timing__hold_r2r_vio__count	0
267	timing__setup_vio__count	0
268	timing__setup_r2r__ws	0.073893
269	timing__setup_r2r_vio__count	0
270	timing__unannotated_net__count	1413
271	timing__unannotated_net_filtered__count	0
272	design__xor_difference__count	0
273	magic__drc_error__count	55
274	klayout__drc_error__count	0
275	magic__illegal_overlap__count	0
276	design__lvs_device_difference__count	3
277	design__lvs_net_difference__count	2
278	design__lvs_property_fail__count	0
279	design__lvs_error__count	196
280	design__lvs_unmatched_device__count	21
281	design__lvs_unmatched_net__count	93
282	design__lvs_unmatched_pin__count	77