mirror of https://github.com/efabless/caravel.git
105 lines
3.8 KiB
Tcl
105 lines
3.8 KiB
Tcl
# Power nets
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if { ! [info exists ::env(VDD_NET)] } {
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set ::env(VDD_NET) $::env(VDD_PIN)
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}
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if { ! [info exists ::env(GND_NET)] } {
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set ::env(GND_NET) $::env(GND_PIN)
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}
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set ::power_nets $::env(VDD_NET)
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set ::ground_nets $::env(GND_NET)
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if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
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if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
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foreach power_pin $::env(STD_CELL_POWER_PINS) {
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add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
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}
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foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
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add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
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}
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}
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}
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set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
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# Assesses whether the deisgn is the core of the chip or not based on the
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# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
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define_pdn_grid \
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-name stdcell_grid \
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-starts_with POWER \
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-voltage_domain CORE \
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-pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_LOWER_LAYER) \
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-width $::env(FP_PDN_VWIDTH) \
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-pitch $::env(FP_PDN_VPITCH) \
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-offset $::env(FP_PDN_VOFFSET) \
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-starts_with POWER
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add_pdn_stripe \
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-grid stdcell_grid \
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-layer $::env(FP_PDN_UPPER_LAYER) \
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-width $::env(FP_PDN_HWIDTH) \
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-pitch $::env(FP_PDN_HPITCH) \
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-offset $::env(FP_PDN_HOFFSET) \
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-starts_with POWER
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add_pdn_connect \
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-grid stdcell_grid \
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-layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
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# Adds the standard cell rails if enabled.
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if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
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add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
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add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
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}
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# Adds the core ring if enabled.
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if { $::env(FP_PDN_CORE_RING) == 1 } {
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add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
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-widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
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-spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
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-core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
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}
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if { $::env(VDD_NET) == "vccd1" } {
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add_global_connection -net vccd1 -inst_pattern gpio_logic_high -pin_pattern vccd1
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add_global_connection -net vssd1 -inst_pattern gpio_logic_high -pin_pattern vssd1
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define_pdn_grid \
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-macro \
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-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
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add_pdn_connect \
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-layers { met4_PIN_ver met5 }
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# set macro {
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# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
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# power_pins "vccd1"
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# ground_pins "vssd1"
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# blockages "met1 met2 met3 met4 met5"
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# straps {
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# }
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# connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
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# }
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# pdngen::specify_grid macro [subst $macro]
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set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
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} else {
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# set macro {
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# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
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# power_pins "vccd1"
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# ground_pins "vssd1"
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# blockages "met1 met2 met3 met4 met5"
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# straps {
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# }
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# }
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# pdngen::specify_grid macro [subst $macro]
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define_pdn_grid \
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-macro \
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-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
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set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
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}
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# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
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set ::rails_start_with "POWER" ;
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# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
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set ::stripes_start_with "POWER" ;
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