kareem b70c27c69f REVERT ME: temporarily match simple_por pin in verilog with lef		2022-04-01 10:52:36 -07:00
..
dv	Added a testbench that exercises the SRAM 2nd (read-only) port, as	2021-12-29 11:24:17 -05:00
gl	Corrected the gen_gpio_defaults.py script so that it behaves	2021-12-29 15:42:41 -05:00
rtl	REVERT ME: temporarily match simple_por pin in verilog with lef	2022-04-01 10:52:36 -07:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00