caravel/verilog
manarabdelaty b5fe87304a [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00
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dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
rtl [RTL] Fix power connection to HK/digital_pll/caravel clocking, also fix resetb connection 2021-11-17 13:17:23 +02:00