manarabdelaty aa766f9144 [DATA] Update caravel_clocking module		2021-12-05 19:44:28 +02:00
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dv	Update storage testbench to work with one 2K block	2021-11-12 17:14:21 +02:00
gl	[DATA] Update caravel_clocking module	2021-12-05 19:44:28 +02:00
rtl	Changed the synchronized reset to occur on the clock falling edge	2021-12-02 14:26:59 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00