mirror of https://github.com/efabless/caravel.git
401 lines
11 KiB
Verilog
401 lines
11 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// `default_nettype none
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module chip_io(
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// Package Pins
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inout vddio_pad, // Common padframe/ESD supply
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inout vddio_pad2,
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inout vssio_pad, // Common padframe/ESD ground
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inout vssio_pad2,
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inout vccd_pad, // Common 1.8V supply
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inout vssd_pad, // Common digital ground
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inout vdda_pad, // Management analog 3.3V supply
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inout vssa_pad, // Management analog ground
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inout vdda1_pad, // User area 1 3.3V supply
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inout vdda1_pad2,
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inout vdda2_pad, // User area 2 3.3V supply
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inout vssa1_pad, // User area 1 analog ground
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inout vssa1_pad2,
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inout vssa2_pad, // User area 2 analog ground
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inout vccd1_pad, // User area 1 1.8V supply
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inout vccd2_pad, // User area 2 1.8V supply
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inout vssd1_pad, // User area 1 digital ground
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inout vssd2_pad, // User area 2 digital ground
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// Core Side
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inout vddio, // Common padframe/ESD supply
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inout vssio, // Common padframe/ESD ground
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inout vccd, // Common 1.8V supply
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inout vssd, // Common digital ground
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inout vdda, // Management analog 3.3V supply
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inout vssa, // Management analog ground
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8V supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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inout gpio,
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input clock,
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input resetb,
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output flash_csb,
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output flash_clk,
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inout flash_io0,
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inout flash_io1,
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// Chip Core Interface
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input porb_h,
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input por,
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output resetb_core_h,
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output clock_core,
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input gpio_out_core,
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output gpio_in_core,
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input gpio_mode0_core,
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input gpio_mode1_core,
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input gpio_outenb_core,
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input gpio_inenb_core,
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input flash_csb_core,
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input flash_clk_core,
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input flash_csb_oeb_core,
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input flash_clk_oeb_core,
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input flash_io0_oeb_core,
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input flash_io1_oeb_core,
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input flash_csb_ieb_core, // NOTE: unused, fix me!
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input flash_clk_ieb_core, // NOTE: unused, fix me!
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input flash_io0_ieb_core,
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input flash_io1_ieb_core,
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input flash_io0_do_core,
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input flash_io1_do_core,
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output flash_io0_di_core,
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output flash_io1_di_core,
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// User project IOs
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inout [`MPRJ_IO_PADS-1:0] mprj_io,
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input [`MPRJ_IO_PADS-1:0] mprj_io_out,
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input [`MPRJ_IO_PADS-1:0] mprj_io_oeb,
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input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
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input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
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input [`MPRJ_IO_PADS-1:0] mprj_io_vtrip_sel,
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input [`MPRJ_IO_PADS-1:0] mprj_io_slow_sel,
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input [`MPRJ_IO_PADS-1:0] mprj_io_holdover,
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input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
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input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
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input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
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input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
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output [`MPRJ_IO_PADS-1:0] mprj_io_in,
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// User project direct access to gpio pad connections for analog
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// (all but the lowest-numbered 7 pads)
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inout [`MPRJ_IO_PADS-10:0] mprj_analog_io
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);
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// To be considered: Master hold signal on all user pads (?)
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// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
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// and setting enh to porb_h.
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wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
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wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
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assign mprj_io_hldh_n = {`MPRJ_IO_PADS{vddio}};
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assign mprj_io_enh = {`MPRJ_IO_PADS{porb_h}};
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wire analog_a, analog_b;
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wire vddio_q, vssio_q;
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// Instantiate power and ground pads for management domain
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// 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
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// One each HV and LV clamp.
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// HV clamps connect between one HV power rail and one ground
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// LV clamps have two clamps connecting between any two LV power
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// rails and grounds, and one back-to-back diode which connects
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// between the first LV clamp ground and any other ground.
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sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[0] (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDIO_PAD(vddio_pad)
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`endif
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);
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// lies in user area 2
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sky130_ef_io__vddio_hvc_clamped_pad \mgmt_vddio_hvclamp_pad[1] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDIO_PAD(vddio_pad2)
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`endif
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);
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sky130_ef_io__vdda_hvc_clamped_pad mgmt_vdda_hvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda_pad)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped_pad mgmt_vccd_lvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd_pad)
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`endif
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);
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sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[0] (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSIO_PAD(vssio_pad)
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`endif
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);
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sky130_ef_io__vssio_hvc_clamped_pad \mgmt_vssio_hvclamp_pad[1] (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSIO_PAD(vssio_pad2)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad mgmt_vssa_hvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa_pad)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped_pad mgmt_vssd_lvclamp_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd_pad)
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`endif
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);
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// Instantiate power and ground pads for user 1 domain
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// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
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sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda1_pad)
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`endif
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);
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sky130_ef_io__vdda_hvc_clamped_pad \user1_vdda_hvclamp_pad[1] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda1_pad2)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
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`USER1_ABUTMENT_PINS
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.VCCD1(vccd1),
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.VSSD1(vssd1),
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd1_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[0] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa1_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad \user1_vssa_hvclamp_pad[1] (
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`USER1_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa1_pad2)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
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`USER1_ABUTMENT_PINS
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.VCCD1(vccd1),
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.VSSD1(vssd1),
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd1_pad)
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`endif
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);
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// Instantiate power and ground pads for user 2 domain
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// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
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sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VDDA_PAD(vdda2_pad)
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`endif
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);
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sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
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`USER2_ABUTMENT_PINS
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.VCCD1(vccd2),
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.VSSD1(vssd2),
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`ifndef TOP_ROUTING
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.VCCD_PAD(vccd2_pad)
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`endif
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);
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sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
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`USER2_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.VSSA_PAD(vssa2_pad)
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`endif
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);
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sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
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`USER2_ABUTMENT_PINS
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.VCCD1(vccd2),
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.VSSD1(vssd2),
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`ifndef TOP_ROUTING
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.VSSD_PAD(vssd2_pad)
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`endif
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);
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wire [2:0] dm_all =
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{gpio_mode1_core, gpio_mode1_core, gpio_mode0_core};
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wire[2:0] flash_io0_mode =
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{flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
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wire[2:0] flash_io1_mode =
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{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
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// Management clock input pad
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`INPUT_PAD(clock, clock_core);
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// Management GPIO pad
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`INOUT_PAD(gpio, gpio_in_core, gpio_out_core, gpio_inenb_core, gpio_outenb_core, dm_all);
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// Management Flash SPI pads
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`INOUT_PAD(flash_io0, flash_io0_di_core, flash_io0_do_core, flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
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`INOUT_PAD(flash_io1, flash_io1_di_core, flash_io1_do_core, flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
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`OUTPUT_NO_INP_DIS_PAD(flash_csb, flash_csb_core, flash_csb_oeb_core);
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`OUTPUT_NO_INP_DIS_PAD(flash_clk, flash_clk_core, flash_clk_oeb_core);
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// NOTE: The analog_out pad from the raven chip has been replaced by
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// the digital reset input resetb on caravel due to the lack of an on-board
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// power-on-reset circuit. The XRES pad is used for providing a glitch-
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// free reset.
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wire xresloop;
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sky130_fd_io__top_xres4v2 resetb_pad (
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`MGMT_ABUTMENT_PINS
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`ifndef TOP_ROUTING
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.PAD(resetb),
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`endif
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.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
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.TIE_HI_ESD(),
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.TIE_LO_ESD(),
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.PAD_A_ESD_H(xresloop),
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.XRES_H_N(resetb_core_h),
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.DISABLE_PULLUP_H(vssio), // 0 = enable pull-up on reset pad
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.ENABLE_H(porb_h), // Power-on-reset
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.EN_VDDIO_SIG_H(vssio), // No idea.
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.INP_SEL_H(vssio), // 1 = use filt_in_h else filter the pad input
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.FILT_IN_H(vssio), // Alternate input for glitch filter
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.PULLUP_H(vssio), // Pullup connection for alternate filter input
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.ENABLE_VDDIO(vccd)
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);
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// Corner cells (These are overlay cells; it is not clear what is normally
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// supposed to go under them.)
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sky130_ef_io__corner_pad mgmt_corner [1:0] (
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`ifndef TOP_ROUTING
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.VSSIO(vssio),
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.VDDIO(vddio),
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.VDDIO_Q(vddio_q),
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.VSSIO_Q(vssio_q),
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.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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.VSSA(vssa),
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.VSWITCH(vddio),
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.VDDA(vdda),
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.VCCD(vccd),
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.VCCHIB(vccd)
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`endif
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);
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sky130_ef_io__corner_pad user1_corner (
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`ifndef TOP_ROUTING
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.VSSIO(vssio),
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.VDDIO(vddio),
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.VDDIO_Q(vddio_q),
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.VSSIO_Q(vssio_q),
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.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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.VSSA(vssa1),
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.VSWITCH(vddio),
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.VDDA(vdda1),
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.VCCD(vccd),
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.VCCHIB(vccd)
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`endif
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);
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sky130_ef_io__corner_pad user2_corner (
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`ifndef TOP_ROUTING
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.VSSIO(vssio),
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.VDDIO(vddio),
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.VDDIO_Q(vddio_q),
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.VSSIO_Q(vssio_q),
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.AMUXBUS_A(analog_a),
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.AMUXBUS_B(analog_b),
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.VSSD(vssd),
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.VSSA(vssa2),
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.VSWITCH(vddio),
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.VDDA(vdda2),
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.VCCD(vccd),
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.VCCHIB(vccd)
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`endif
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);
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mprj_io mprj_pads(
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.vddio(vddio),
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.vssio(vssio),
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.vccd(vccd),
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.vssd(vssd),
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.vdda1(vdda1),
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.vdda2(vdda2),
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.vssa1(vssa1),
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.vssa2(vssa2),
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.vddio_q(vddio_q),
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.vssio_q(vssio_q),
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.analog_a(analog_a),
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.analog_b(analog_b),
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.porb_h(porb_h),
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.io(mprj_io),
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.io_out(mprj_io_out),
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.oeb(mprj_io_oeb),
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.hldh_n(mprj_io_hldh_n),
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.enh(mprj_io_enh),
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.inp_dis(mprj_io_inp_dis),
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.ib_mode_sel(mprj_io_ib_mode_sel),
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.vtrip_sel(mprj_io_vtrip_sel),
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.holdover(mprj_io_holdover),
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.slow_sel(mprj_io_slow_sel),
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.analog_en(mprj_io_analog_en),
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.analog_sel(mprj_io_analog_sel),
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.analog_pol(mprj_io_analog_pol),
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.dm(mprj_io_dm),
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.io_in(mprj_io_in),
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.analog_io(mprj_analog_io)
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);
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endmodule
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// `default_nettype wire
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