Tim Edwards be56cb19ed Modified the GPIO control block to put additional delay on the data ... output of each GPIO block to overcome any wiring delays between GPIO blocks that could potentially cause hold violations.		2022-03-21 12:07:12 -04:00
..
dv	Added a testbench that exercises the SRAM 2nd (read-only) port, as	2021-12-29 11:24:17 -05:00
gl	Corrected the gen_gpio_defaults.py script so that it behaves	2021-12-29 15:42:41 -05:00
rtl	Modified the GPIO control block to put additional delay on the data	2022-03-21 12:07:12 -04:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00