Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing ... connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.		2021-12-07 10:06:35 -05:00
..
dv	Fixed one bad error in clock_div which had been done without my	2021-12-06 21:37:51 -05:00
gl	Corrected an error in verilog/gl/chip_io_alt.v, which was missing	2021-12-07 10:06:35 -05:00
rtl	Corrected an inadvertant error in caravel_netlists.v that prevents	2021-12-07 09:14:59 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00