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caravel
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caravel/verilog
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Tim Edwards 767342e183 Added a completely revised sysctrl testbench based on accessing the 
housekeeping SPI through the back-door wishbone interface.  Checks
most of the SPI registers (but could do more).
 		2021-10-19 17:32:20 -04:00
..
dv/caravel Added a completely revised sysctrl testbench based on accessing the 2021-10-19 17:32:20 -04:00
rtl Added a completely revised sysctrl testbench based on accessing the 2021-10-19 17:32:20 -04:00