caravel/final_summary_report.csv at 72b2c724c91a6023086ba615f2afab6ac94f0357

1		design	design_name	config	flow_status	total_runtime	routed_runtime	(Cell/mm^2)/Core_Util	DIEAREA_mm^2	CellPer_mm^2	OpenDP_Util	Peak_Memory_Usage_MB	cell_count	tritonRoute_violations	Short_violations	MetSpc_violations	OffGrid_violations	MinHole_violations	Other_violations	Magic_violations	antenna_violations	lvs_total_errors	cvc_total_errors	klayout_violations	wire_length	vias	wns	pl_wns	optimized_wns	fastroute_wns	spef_wns	tns	pl_tns	optimized_tns	fastroute_tns	spef_tns	HPWL	routing_layer1_pct	routing_layer2_pct	routing_layer3_pct	routing_layer4_pct	routing_layer5_pct	routing_layer6_pct	wires_count	wire_bits	public_wires_count	public_wire_bits	memories_count	memory_bits	processes_count	cells_pre_abc	AND	DFF	NAND	NOR	OR	XOR	XNOR	MUX	inputs	outputs	level	EndCaps	TapCells	Diodes	Total_Physical_Cells	suggested_clock_frequency	suggested_clock_period	CLOCK_PERIOD	SYNTH_STRATEGY	SYNTH_MAX_FANOUT	FP_CORE_UTIL	FP_ASPECT_RATIO	FP_PDN_VPITCH	FP_PDN_HPITCH	PL_TARGET_DENSITY	GLB_RT_ADJUSTMENT	STD_CELL_LIBRARY	CELL_PAD	DIODE_INSERTION_STRATEGY
2	0	/project/openlane/caravel_clocking	caravel_clocking	caravel_clocking	flow_completed	0h2m5s	-1	83437.5	0.0064	41718.75	89.0	668.91	267	0	0	0	0	0	0	0	0	0	0	-1	5362	2031	-3.73	-5.41	-1	-5.06	-1	-24.41	-36.66	-1	-29.74	-1	2636042.0	22.97	25.9	15.17	0.43	0.0	-1	202	252	67	117	0	0	0	200	0	0	0	0	0	0	0	4	72	71	6	42	57	0	99	90.9090909090909	11.0	10.0	DELAY 0	5	50	1	22.986666666666668	19.413333333333334	0.94	0	sky130_fd_sc_hd	0	4