caravel/verilog
kareem 71e309a923 some rtl changes
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
2022-10-10 05:13:48 -07:00
..
dv Corrected the pull-up definition and revised the CSB definition to 2022-10-05 10:02:24 -04:00
gl reharden!: caravel 2022-10-10 04:51:05 -07:00
rtl some rtl changes 2022-10-10 05:13:48 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00