caravel/verilog/dv
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
..
caravel Fixed one bad error in clock_div which had been done without my 2021-12-06 21:37:51 -05:00
wb_utests Corrected the two failing testbenches (which needed fixing because 2021-10-28 22:20:46 -04:00
README.md adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
dummy_slave.v adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00

README.md

DV Tests

Organized into two subdirectories:

  • caravel: contains tests for both the mangement SoC and an example user project.
  • wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
├── caravel
│   ├── mgmt_soc
│   ├── user_proj_example
└── wb_utests