caravel/signoff/mprj2_logic_high/final_summary_report.csv

1.4 KiB

1designdesign_nameconfigflow_statustotal_runtimerouted_runtime(Cell/mm^2)/Core_UtilDIEAREA_mm^2CellPer_mm^2OpenDP_UtilPeak_Memory_Usage_MBcell_counttritonRoute_violationsShort_violationsMetSpc_violationsOffGrid_violationsMinHole_violationsOther_violationsMagic_violationsantenna_violationslvs_total_errorscvc_total_errorsklayout_violationswire_lengthviaswnspl_wnsoptimized_wnsfastroute_wnsspef_wnstnspl_tnsoptimized_tnsfastroute_tnsspef_tnsHPWLrouting_layer1_pctrouting_layer2_pctrouting_layer3_pctrouting_layer4_pctrouting_layer5_pctrouting_layer6_pctwires_countwire_bitspublic_wires_countpublic_wire_bitsmemories_countmemory_bitsprocesses_countcells_pre_abcANDDFFNANDNORORXORXNORMUXinputsoutputslevelEndCapsTapCellsDiodesTotal_Physical_Cellssuggested_clock_frequencysuggested_clock_periodCLOCK_PERIODSYNTH_STRATEGYSYNTH_MAX_FANOUTFP_CORE_UTILFP_ASPECT_RATIOFP_PDN_VPITCHFP_PDN_HPITCHPL_TARGET_DENSITYGLB_RT_ADJUSTMENTSTD_CELL_LIBRARYCELL_PADDIODE_INSERTION_STRATEGY
20/project/openlane/mprj2_logic_highmprj2_logic_highmprj2_logic_highflow_completed0h0m51s-12857.1428571428580.00071428.571428571429-1443.0210-1-1-1-100-100-13930.0-1-10.0-10.0-1-10.0-1-10.00.00.03.42-13.421111000100000004-1-1-141401890.909090909090911.010.0AREA 05501405.80.550.0sky130_fd_sc_hd43