mirror of https://github.com/efabless/caravel.git
52 lines
1.7 KiB
Plaintext
52 lines
1.7 KiB
Plaintext
*---------------------------------------------------------------------------
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* SPDX-License-Identifier: Apache-2.0
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*---------------------------------------------------------------------------
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* Simple POR circuit for Caravel
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*-------------------------------------------------------------------
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*
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* Architecture: see simple_por.spice
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* Response of this circuit by ngspice simulation is a ~15ms delay.
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*-------------------------------------------------------------------
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.lib /home/tim/projects/efabless/tech/SW/sky130A/libs.tech/ngspice/sky130.lib.spice tt
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.include /home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
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.include simple_por.spice
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*----------------------------
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* Testbench circuit
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*----------------------------
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Vpwr vdda vss DC=0 PWL(0.0 0 100u 0 5m 3.3)
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Vdig vccd vss DC=0 PWL(0.0 0 300u 0 5.3m 1.8)
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Rgnd vss 0 0.01
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Cload1 porb_h vss 1E-12
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Cload2 por_l vss 1E-12
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Cload3 porb_l vss 1E-12
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Xpor vdda vccd vss porb_h por_l porb_l simple_por
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*----------------------------
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*----------------------------
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* Testbench control
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*----------------------------
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.control
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tran 10u 20m
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plot porb_h
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plot por_l
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plot porb_l
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.endc
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.end
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