caravel/signoff/digital_pll/metrics.csv

1.7 KiB

1designdesign_nameconfigflow_statustotal_runtimerouted_runtime(Cell/mm^2)/Core_UtilDIEAREA_mm^2CellPer_mm^2OpenDP_UtilPeak_Memory_Usage_MBcell_counttritonRoute_violationsShort_violationsMetSpc_violationsOffGrid_violationsMinHole_violationsOther_violationsMagic_violationsantenna_violationslvs_total_errorscvc_total_errorsklayout_violationswire_lengthviaswnspl_wnsoptimized_wnsfastroute_wnsspef_wnstnspl_tnsoptimized_tnsfastroute_tnsspef_tnsHPWLrouting_layer1_pctrouting_layer2_pctrouting_layer3_pctrouting_layer4_pctrouting_layer5_pctrouting_layer6_pctwires_countwire_bitspublic_wires_countpublic_wire_bitsmemories_countmemory_bitsprocesses_countcells_pre_abcANDDFFNANDNORORXORXNORMUXinputsoutputslevelEndCapsTapCellsDiodesTotal_Physical_CellsCoreArea_um^2power_slowest_internal_uWpower_slowest_switching_uWpower_slowest_leakage_uWpower_typical_internal_uWpower_typical_switching_uWpower_typical_leakage_uWpower_fastest_internal_uWpower_fastest_switching_uWpower_fastest_leakage_uWcritical_path_nssuggested_clock_periodsuggested_clock_frequencyCLOCK_PERIODSYNTH_STRATEGYSYNTH_MAX_FANOUTFP_CORE_UTILFP_ASPECT_RATIOFP_PDN_VPITCHFP_PDN_HPITCHPL_TARGET_DENSITYGRT_ADJUSTMENTSTD_CELL_LIBRARYDIODE_INSERTION_STRATEGY
2/home/kareem_farid/caravel/openlane/digital_plldigital_pll22_10_18_06_51flow completed0h1m7s0ms0h0m46s0ms-2.00.0075-167.08534.82-10000000-1-1-1-1840225660.00.0-10.00.00.00.0-10.00.06100018.00.028.6922.890.650.00.0580776121305000614531711297191227567013467501215554.0768-1-1-1-1-1-1-1-1-1-110.0100.010.0AREA 0750140400.680sky130_fd_sc_hd4