..
__uprj_analog_netlists.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
__uprj_netlists.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
__user_project_wrapper.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
caravan.v
A number of changes to the caravan netlists, (1) to correct for
2021-11-22 09:46:21 -05:00
caravan_netlists.v
A number of changes to the caravan netlists, (1) to correct for
2021-11-22 09:46:21 -05:00
caravan_openframe.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
caravel.v
Several more LVS corrections, including fixing a label in chip_io that
2021-11-21 22:58:39 -05:00
caravel_clocking.v
[RTL] Move inverter from top level to HK
2021-11-16 13:59:17 +02:00
caravel_netlists.v
Removed two references for single-macro verilog files that are no
2021-11-15 17:53:48 -05:00
caravel_openframe.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
chip_io.v
A number of changes to the caravan netlists, (1) to correct for
2021-11-22 09:46:21 -05:00
chip_io_alt.v
A number of changes to the caravan netlists, (1) to correct for
2021-11-22 09:46:21 -05:00
clock_div.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
defines.v
Update storage testbench to work with one 2K block
2021-11-12 17:14:21 +02:00
digital_pll.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
digital_pll_controller.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
gpio_control_block.v
(1) Corrected an error from a recent commit where the reset was
2021-11-03 23:18:36 -04:00
gpio_defaults_block.v
Implemented a system for setting the GPIO power-on defaults through
2021-10-23 17:18:30 -04:00
gpio_logic_high.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
housekeeping.v
[RTL] Move inverter from top level to HK
2021-11-16 13:59:17 +02:00
housekeeping_spi.v
Modified the housekeeping SPI to generate a read strobe (or rather
2021-10-23 22:06:24 -04:00
mgmt_protect.v
Revised the management protect block to include protections against
2021-10-27 19:36:43 -04:00
mgmt_protect_hv.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
mprj2_logic_high.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
mprj_io.v
Modified the padframe definition to keep the vccd domain continuous
2021-11-03 10:53:09 -04:00
mprj_logic_high.v
Revised the management protect block to include protections against
2021-10-27 19:36:43 -04:00
pads.v
Modified the padframe definition to keep the vccd domain continuous
2021-11-03 10:53:09 -04:00
ring_osc2x13.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
simple_por.v
Seeding with documentation of pinout and verilog RTL (mostly unchanged
2021-10-12 16:31:42 -04:00
user_defines.v
Split the layout of the GPIO defaults block into three versions, for the
2021-11-06 13:28:26 -04:00
user_id_programming.v
Implemented a system for setting the GPIO power-on defaults through
2021-10-23 17:18:30 -04:00
xres_buf.v
Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
2021-10-31 21:43:09 -04:00
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