caravel/verilog
Tim Edwards cfeb62dfb4 A number of changes to the caravan netlists, (1) to correct for
problems that had been fixed recently in caravel, and which cause
the caravan testbench to break, but which were not noticed;  (2)
corrected the count of gpio_control_block modules, which was one
off, with two of them overlapping (not sure how that even passes
simulation, but it did);  (3) fixed a power connection in the
caravel chip_io, which should have caused chip_io to fail LVS,
so apparently LVS was not run on chip_io. . .
2021-11-22 09:46:21 -05:00
..
dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
rtl A number of changes to the caravan netlists, (1) to correct for 2021-11-22 09:46:21 -05:00