passant5 e067e558a3 update `digital_pll` and `caravel_clocking` sdc pll clocks constraints (#293) ... * update pll clocks period constraint to `11.76ns (85MHz)` instead of `6.6667ns (150 MHz)` * update sdcs Rev and date		2022-10-21 07:45:56 -07:00
..
openlane-signoff	reharden: digital_pll	2022-10-18 07:07:32 -07:00
primetime-signoff	add signoff results for `digital_pll`:	2022-10-19 07:05:38 -07:00
standalone_pvr	add signoff results for `digital_pll`:	2022-10-19 07:05:38 -07:00
OPENLANE_VERSION	reharden: digital_pll	2022-10-13 06:21:08 -07:00
PDK_SOURCES	reharden: digital_pll	2022-10-13 06:21:08 -07:00
digital_pll.sdc	update `digital_pll` and `caravel_clocking` sdc pll clocks constraints (#293)	2022-10-21 07:45:56 -07:00
final_summary_report.csv	[DATA] Update digital_pll	2021-12-07 13:19:02 +02:00
metrics.csv	reharden: digital_pll	2022-10-18 07:07:32 -07:00
signoff.rpt	add signoff results for `digital_pll`:	2022-10-19 07:05:38 -07:00