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riscv
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caravel
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https://github.com/efabless/caravel.git
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40c7776b57
caravel
/
verilog
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Marwan Abbas
40c7776b57
added power connection to buffer rtl
2022-10-15 12:56:40 +02:00
..
dv
resolve conflict
2022-10-13 12:11:42 -07:00
gl
add housekeeping views
2022-10-14 09:26:34 -07:00
rtl
added power connection to buffer rtl
2022-10-15 12:56:40 +02:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00