Tim Edwards 3a57940371 Revised the management protect block to include protections against ... an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).		2021-10-27 19:36:43 -04:00
..
__uprj_analog_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__uprj_netlists.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_analog_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
__user_project_wrapper.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravan.v	Revised the management protect block to include protections against	2021-10-27 19:36:43 -04:00
caravan_netlists.v	Updated the caravan netlist and implemented the caravan testbench.	2021-10-25 15:08:13 -04:00
caravan_openframe.v	Created an "open frame" version of caravan (and revised the one for	2021-10-25 16:29:12 -04:00
caravel.v	Revised the management protect block to include protections against	2021-10-27 19:36:43 -04:00
caravel_clocking.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
caravel_netlists.v	Updated the caravan netlist and implemented the caravan testbench.	2021-10-25 15:08:13 -04:00
caravel_openframe.v	Created an "open frame" version of caravan (and revised the one for	2021-10-25 16:29:12 -04:00
chip_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
chip_io_alt.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
clock_div.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
defines.v	Correction to the mprj_bitbang testbench to run the test without running	2021-10-21 10:57:20 -04:00
digital_pll.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
digital_pll_controller.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
gpio_control_block.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
gpio_defaults_block.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00
gpio_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
housekeeping.v	Update to the back-door wishbone access to housekeeping to better	2021-10-24 16:58:47 -04:00
housekeeping_spi.v	Modified the housekeeping SPI to generate a read strobe (or rather	2021-10-23 22:06:24 -04:00
mgmt_protect.v	Revised the management protect block to include protections against	2021-10-27 19:36:43 -04:00
mgmt_protect_hv.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj2_logic_high.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_io.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
mprj_logic_high.v	Revised the management protect block to include protections against	2021-10-27 19:36:43 -04:00
pads.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
ring_osc2x13.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
simple_por.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v	Seeding with documentation of pinout and verilog RTL (mostly unchanged	2021-10-12 16:31:42 -04:00
user_defines.v	Removed unused definitions from user_defines.v, and added more	2021-10-25 16:36:18 -04:00
user_id_programming.v	Implemented a system for setting the GPIO power-on defaults through	2021-10-23 17:18:30 -04:00