caravel/verilog
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
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dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
rtl Fixed another missing line from the management protect block call 2021-11-18 08:25:13 -05:00