riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
caravel/verilog
History
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
..
dv Update storage testbench to work with one 2K block 2021-11-12 17:14:21 +02:00
gl [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
rtl Fixed another missing line from the management protect block call 2021-11-18 08:25:13 -05:00