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__uprj_analog_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__uprj_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_analog_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravan.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravan_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravel.v
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Additional corrections, mostly to the housekeeping module. The
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2021-10-17 21:38:40 -04:00 |
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caravel_clocking.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravel_netlists.v
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First major update; current code passes syntax checks in iverilog
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2021-10-15 21:49:49 -04:00 |
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caravel_openframe.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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chip_io.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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chip_io_alt.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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clock_div.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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defines.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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digital_pll.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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digital_pll_controller.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_control_block.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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housekeeping.v
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Added and debugged two more testbenches, gpio_mgmt and hkspi.
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2021-10-18 11:25:26 -04:00 |
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housekeeping_spi.v
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First major update; current code passes syntax checks in iverilog
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2021-10-15 21:49:49 -04:00 |
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mgmt_protect.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mgmt_protect_hv.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj2_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj_io.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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pads.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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ring_osc2x13.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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simple_por.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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user_id_programming.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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