caravel/verilog
kareem 9ccb0ff2ed reharden!: caravel
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
2022-10-12 04:45:08 -07:00
..
dv added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
gl reharden!: caravel 2022-10-12 04:45:08 -07:00
rtl Merge pull request #165 from efabless/misc-rtl-changes 2022-10-11 10:48:18 +02:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00