caravel/verilog
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
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dv add test uart_rx 2022-10-01 02:23:47 -07:00
gl reharden!: gpio_control_block 2022-09-27 07:09:26 -07:00
rtl Add RTL for 2 debug regs used to test and located inside user_project_wrapper 2022-09-30 03:52:34 -07:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00