caravel/signoff/digital_pll/metrics.csv

1	design	design_name	config	flow_status	total_runtime	routed_runtime	(Cell/mm^2)/Core_Util	DIEAREA_mm^2	CellPer_mm^2	OpenDP_Util	Peak_Memory_Usage_MB	cell_count	tritonRoute_violations	Short_violations	MetSpc_violations	OffGrid_violations	MinHole_violations	Other_violations	Magic_violations	antenna_violations	lvs_total_errors	cvc_total_errors	klayout_violations	wire_length	vias	wns	pl_wns	optimized_wns	fastroute_wns	spef_wns	tns	pl_tns	optimized_tns	fastroute_tns	spef_tns	HPWL	routing_layer1_pct	routing_layer2_pct	routing_layer3_pct	routing_layer4_pct	routing_layer5_pct	routing_layer6_pct	wires_count	wire_bits	public_wires_count	public_wire_bits	memories_count	memory_bits	processes_count	cells_pre_abc	AND	DFF	NAND	NOR	OR	XOR	XNOR	MUX	inputs	outputs	level	EndCaps	TapCells	Diodes	Total_Physical_Cells	CoreArea_um^2	power_slowest_internal_uW	power_slowest_switching_uW	power_slowest_leakage_uW	power_typical_internal_uW	power_typical_switching_uW	power_typical_leakage_uW	power_fastest_internal_uW	power_fastest_switching_uW	power_fastest_leakage_uW	critical_path_ns	suggested_clock_period	suggested_clock_frequency	CLOCK_PERIOD	SYNTH_STRATEGY	SYNTH_MAX_FANOUT	FP_CORE_UTIL	FP_ASPECT_RATIO	FP_PDN_VPITCH	FP_PDN_HPITCH	PL_TARGET_DENSITY	GRT_ADJUSTMENT	STD_CELL_LIBRARY	DIODE_INSERTION_STRATEGY
2	/home/kareem_farid/caravel/openlane/digital_pll	digital_pll	22_10_17_10_45	flow completed	0h1m38s0ms	0h1m17s0ms	-2.0	0.005625	-1	92.39	549.09	-1	0	0	0	0	0	0	0	-1	-1	-1	-1	7617	2598	0.0	0.0	-1	0.0	0.0	0.0	0.0	-1	0.0	0.0	4636055.0	0.0	31.89	31.26	0.0	0.0	0.0	580	776	121	305	0	0	0	614	5	3	17	11	297	19	12	27	56	70	13	46	50	0	96	4000.0864	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	10.0	100.0	10.0	AREA 0	7	50	1	40	40	0.94	0	sky130_fd_sc_hd	4