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caravel
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05278ec738
caravel
/
verilog
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manarabdelaty
05278ec738
[DATA] Update HK views (timing clean)
2021-11-25 12:54:22 +02:00
..
dv
Update storage testbench to work with one 2K block
2021-11-12 17:14:21 +02:00
gl
[DATA] Update HK views (timing clean)
2021-11-25 12:54:22 +02:00
rtl
Revised the spare logic block to make sure that all inputs are
2021-11-24 09:34:52 -05:00
stubs
[DATA] Add spare_logic_block
2021-11-24 20:36:23 +02:00