consistent (all metal2 pins the same width and length and all
metal3 pins the same width and length). The PR boundary was
moved back to where it was, 0.28um from the pin ends; that
causes overlap with the padframe but should not be an issue since
the openframe wrapper is manually placed. All pins reach from
0.28um inside the boundary to the bottom of the comment layer
(which is 2um wide). Some remaining pins which were not on a
10nm grid were corrected.
cells are replaced with the base cells. Routing to pins
is instead done in the "gpio_connects" cells while
improving on the original routing (fewer cross-overs,
multiple vias per contact, wider buses for the analog
signals). Made small adjustments to many of the openframe
wrapper pins to keep them all on a 10nm grid. Moved the
connections previously from the "wrapped" GPIO cell back
from the openframe project border, so that the border can
be clear of all blockages. Added the DEF file of the
wrapper (previously only in the openframe example repo)
to the def/ directory. Note: The modified LVS scripts
depend on the gate-level netlists of the frame, which
have been committed in a prior pull request. This pull
request does not conflict with those files.
Tim Edwards