4 Commits

Author	SHA1	Message	Date
Tim Edwards	6eb8bb54de	Several more LVS corrections, including fixing a label in chip_io that ... got removed from its net by a chang in the LEF view of an I/O pad, and a lack of declaration of an array to attach to pwr_ctrl_out in the verilog, which is valid verilog but netgen can't know the bus size without the no-connect net being declared. The remaining issue has to do with separation of ground domains in the mgmt_protect block.	2021-11-21 22:58:39 -05:00
manarabdelaty	331fdee2bb	[DATA] Update HK module (li1 routing: 249um)	2021-11-20 15:13:16 +02:00
manarabdelaty	53b3a9013e	[DATA] Update HK pin placement	2021-11-19 01:30:14 +02:00
manarabdelaty	56f672bbd8	[DATA] Add HK views	2021-11-15 13:23:54 +02:00