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caravel
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3 Commits

Author SHA1 Message Date
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL 
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
 2021-11-22 22:35:52 -05:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest 
hardened macro components into the caravel and caravan layouts.
 2021-11-15 10:34:52 -05:00