view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
Tim Edwards
manarabdelaty