caravel

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	c3fc004072	Corrected an error in verilog/gl/chip_io_alt.v, which was missing connections to the core side VCCD1 and VSSD1 on the clamped3 pads. Also added scripts for running LVS on chip_io to the mag/ directory, and revised the scripts so that they will only re-run extraction if there is no netlist file in the mag/ directory.	2021-12-07 10:06:35 -05:00
Tim Edwards	2691903104	Reworked part of the layouts of both caravel and caravan to move the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).	2021-12-02 20:45:39 -05:00
Tim Edwards	5262f35610	Modifications done as part of LVS on the caravel top level.	2021-11-21 22:07:16 -05:00

Author

SHA1

Message

Date

Tim Edwards

c3fc004072

Corrected an error in verilog/gl/chip_io_alt.v, which was missing

connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.

2021-12-07 10:06:35 -05:00

Tim Edwards

2691903104

Reworked part of the layouts of both caravel and caravan to move

the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL.  This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).

2021-12-02 20:45:39 -05:00

Tim Edwards

5262f35610

Modifications done as part of LVS on the caravel top level.

2021-11-21 22:07:16 -05:00

3 Commits