verilog gate-level netlists to match the correct GPIO default
value assignments, and modify the top level gate-level caravel.v
and caravan.v netlists to match.
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v. NOTE: user_defines.v ultimately must
reside in the user project. The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
Tim Edwards
jeffdi