Commit Graph

4 Commits

Author SHA1 Message Date
Tim Edwards 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new
caravan logo layout.  Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
2021-11-12 16:12:12 -05:00
Tim Edwards 27fdba364b Added user 1.8V power supply rails to the chip_io and chip_io_alt
layouts.  Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell.  These
internal lines were previously in the power routing cells.
2021-11-10 17:13:43 -05:00
Tim Edwards ba932643e6 Changed the chip_io and chip_io_alt layouts to implement the
continuous ring of vccd and vssd.  The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
2021-11-03 15:57:46 -04:00
Tim Edwards a7148378a0 Added as many of the magic database layout files as are expected to remain
unchanged between the caravel and caravel_openframe repositories.
2021-10-26 10:27:03 -04:00