caravel

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	a8ccbf2890	Added block diagrams for documentation.	2021-10-22 12:01:08 -04:00
Tim Edwards	a15593b217	Added a simple block diagram of the organization of the Caravel harness chip.	2021-10-21 22:40:46 -04:00
Tim Edwards	d0f74db23b	Updated pinout in documentation (doc/README file)	2021-10-20 10:24:41 -04:00
Tim Edwards	184f4a637c	Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and storage. Not all of these pass simulation checks. Added back the bit-bang control of the GPIO programming. Added back the read-only interface between the housekeeping module and the SRAM 2nd port. Revised the memory map text document to reflect the addition of the SRAM ports. There is not yet a testbench for the SRAM read-only interface.	2021-10-19 19:05:47 -04:00
Tim Edwards	767342e183	Added a completely revised sysctrl testbench based on accessing the housekeeping SPI through the back-door wishbone interface. Checks most of the SPI registers (but could do more).	2021-10-19 17:32:20 -04:00
Tim Edwards	2e57b5da08	Added and debugged two more testbenches, gpio_mgmt and hkspi.	2021-10-18 11:25:26 -04:00
Tim Edwards	842200b7ec	Changed the memory map to move the 2e and 2f wishbone domains into the 26 domain (now dedicated to the housekeeping module), with 2e0... now 261... and 2f0... now 262... Although this is not strictly backwards-compatible, the addresses in defs.h have been modified so that C code remains valid with a recompile.	2021-10-16 17:58:36 -04:00
Tim Edwards	bdfa747145	First major update; current code passes syntax checks in iverilog and simulates, but fails testbench (not surprising at this stage).	2021-10-15 21:49:49 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00

9 Commits