4 Commits

Author	SHA1	Message	Date
Tim Edwards	bc9944ce20	Updated the caravan netlist and implemented the caravan testbench.	2021-10-25 15:08:13 -04:00
Tim Edwards	e5c90daddd	Implemented a system for setting the GPIO power-on defaults through ... via programming. The values for each of the GPIOs at power-up are defined in the "user_defines.v" file. For the verilog, they are applied as parameters. For the layout, they will need to be separately defined cells for each of the GPIOs, or at least for each set of unique default values.	2021-10-23 17:18:30 -04:00
Tim Edwards	bdfa747145	First major update; current code passes syntax checks in iverilog ... and simulates, but fails testbench (not surprising at this stage).	2021-10-15 21:49:49 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00