Anton Blanchard
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25e5e27f9d
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Fix issues with port definitions
Caravel fails to build with recent Icarus Verilog versions because some of
the port definitions are not valid.
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2023-01-05 20:53:17 +11:00 |
Tim Edwards
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543fee18e3
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Revised the spare logic block to make sure that all inputs are
reachable from pins on the boundary once it's synthesized.
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2021-11-24 09:34:52 -05:00 |
Tim Edwards
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2b156997cb
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Added a new module with "spare logic" for metal mask fixes.
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2021-11-24 09:23:22 -05:00 |
Tim Edwards
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e86831b188
|
Final edits to make caravel LVS clean.
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2021-11-22 16:51:35 -05:00 |