9 Commits

Author	SHA1	Message	Date
kareem	7e3a33f9d7	chore: add self-review for 3 blocks: ... * gpio_control_block * digital_pll * caravel_clocking	2022-11-01 06:24:08 -07:00
kareem	68063ddadc	reharden: digital_pll ... ~ increase width for more spread decaps + add or cells to cell exclude ~ change placement density in accordance to area ~ change padding to allow for space for decaps	2022-10-18 07:07:32 -07:00
kareem	712b784e16	reharden!: digital_pll ... ~ disable or gate + add nosynth list file	2022-10-17 12:33:25 -07:00
kareem	e5d9788a43	reharden!: digital_pll ... ~ enable synth buffering to fix fanout ~ add *buf_1* to no synth list ~ add attribute (* keep *) to the oscillator as dont touch for yosys !need to verify that the oscillator remains untouched	2022-10-17 10:56:01 -07:00
kareem	ea6badcd67	+ add caravel_clocking & digital_pl & gpio_control_block openlane run config.tcl file	2022-10-14 14:28:47 -07:00
marwaneltoukhy	c83d7b6a52	changed paths of openlane signoff spef and sdfs	2022-10-13 09:11:54 -07:00
kareem	59743f4832	change buf16 to clkbuf16 and reimplement	2022-10-13 06:54:55 -07:00
kareem	0eed96f33f	reharden: digital_pll ... ~ reimplement digital_pll using updated RTL ~ changes in config to generate same PDN ~ change deprecated variables	2022-10-13 06:21:08 -07:00
Passant	78cec109cc	add signoff sdc dir ... move sdc generated from openlane to signoff/<design name>/openlane-signoff rearrange spef directory with RC corners spefs	2022-10-12 07:28:32 -07:00