riscv
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caravel
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4 Commits

Author SHA1 Message Date
M0stafaRady ceac6defa1 fix some tests for gatelevel 2022-10-13 04:05:12 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady 5e523bce5b Add spi master temp created to simulate the silicon validation test and to be removed after 2022-10-04 10:46:34 -07:00
M0stafaRady 79f26f6b38 add new test spi_master_rd 2022-10-03 05:36:36 -07:00