4 Commits

Author	SHA1	Message	Date
Tim Edwards	2691903104	Reworked part of the layouts of both caravel and caravan to move ... the clocking subcircuit from inside the pad area near the "clock" pin to under the DLL. This prevents the DLL from having its outputs travel all the way across the chip to reach the clocking cell and then have the multiplexed clock travel all the way back, especially as the DLL outputs are high-speed signals (up to 150 MHz).	2021-12-02 20:45:39 -05:00
Tim Edwards	fe21089505	Updated caravan with the same addition of four spare logic blocks ... as was made to caravel.	2021-11-24 17:10:05 -05:00
Tim Edwards	08a2c90940	Made updates to correct LVS errors in caravan. Found one major error in the RTL ... verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to correct this; still need to correct the layouts. The error causes the user1 side clock, load, and reset buffers to drive the user2 side as well as the user1 side, making a huge mess of the routing. Will route this by hand.	2021-11-22 22:35:52 -05:00
Tim Edwards	8f75362f82	Start of power routing.	2021-11-20 18:04:43 -05:00