Commit Graph

7 Commits

Author SHA1 Message Date
Tim Edwards e6030f9fb3 Modified the GPIO control block verilog to remove the delay stages
from the data and replace them with a single flop clocked on the
negative edge of the serial clock.  This will completely avoid hold
violations by ensuring that the block's output data bit does not
change anywhere near the clock rising edge, so clocks do not have
to be tightly aligned among all of the GPIO blocks.
2022-07-24 16:17:56 -04:00
Marwan Abbas 14142eb2a1
Fix syntax error in gpio_control_block (#60)
* Fix syntax error in gpio_control_block

Fixed syntax error that was only visible when running iverilog for simulation

* Apply automatic changes to Manifest and README.rst

Co-authored-by: marwaneltoukhy <marwaneltoukhy@users.noreply.github.com>
2022-04-09 00:24:51 -07:00
Kareem Farid 8e02ea79d8
fix wrong cell name
`sky130_fd_sc_hd__dlygate4sd2` is called `sky130_fd_sc_hd__dlygate4sd2_1`
2022-03-22 17:02:36 +02:00
Tim Edwards be56cb19ed Modified the GPIO control block to put additional delay on the data
output of each GPIO block to overcome any wiring delays between
GPIO blocks that could potentially cause hold violations.
2022-03-21 12:07:12 -04:00
Tim Edwards b8dda9c3b1 (1) Corrected an error from a recent commit where the reset was
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping.  (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins.  The load pin propagates through the chaing like the
other two.  Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
2021-11-03 23:18:36 -04:00
Tim Edwards e5c90daddd Implemented a system for setting the GPIO power-on defaults through
via programming.  The values for each of the GPIOs at power-up are
defined in the "user_defines.v" file.  For the verilog, they are
applied as parameters.  For the layout, they will need to be
separately defined cells for each of the GPIOs, or at least for
each set of unique default values.
2021-10-23 17:18:30 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00