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caravel
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4 Commits

Author SHA1 Message Date
Tim Edwards 96ef5c83fd Corrected the corner pad connections to vssd and vccd, which were 
still pointing to vssd1/vccd1/vssd2/vccd2, variously in chip_io.v
and chip_io_alt.v
 2021-11-17 11:44:32 -05:00
Tim Edwards 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally 
deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
 2021-11-15 17:13:43 -05:00
Tim Edwards fe1fcbc3a5 Modified the padframe definition to keep the vccd domain continuous 
around the entire padframe.  The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe.  This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V.  The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
 2021-11-03 10:53:09 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00