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caravel
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13 Commits 140 Branches 61 Tags 15 GiB
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5 Commits

Author SHA1 Message Date
Tim Edwards 33ca4e11ef Additional corrections, mostly to the housekeeping module. The 
top-level simulation now passes the GPIO testbench.
 2021-10-17 21:38:40 -04:00
Tim Edwards 1863a7c529 A number of small corrections. 2021-10-16 23:55:57 -04:00
Tim Edwards 2f74fa83ee Reinstated the logic analyzer as a standard interface for the 
management SoC.
 2021-10-16 17:42:24 -04:00
Tim Edwards bdfa747145 First major update; current code passes syntax checks in iverilog 
and simulates, but fails testbench (not surprising at this stage).
 2021-10-15 21:49:49 -04:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00