* reharden: caravel
~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing
* update pdn for `caravel_clocking` & `digital_pll`
* added script to update and generate the power routing views
* ~ run update_power_routing_views from the caravel root with prboundary
* fix output message
* added power routing lef, mag and gds
* fix update_power_routing_views saving wrong cell name
* reharden: caravel
~ incorperate pdn changes
~ re-extract spefs
* fix caravel_power_routing views
* fix abs path in maglef views
* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect
* generate a new chip_io gds
* regenerate gpio_control_block due to mag and gds not in sync
* reharden: caravel
~ change config to pass clean routing
~ use updated views of macros
* lvs clean views
* add caravel top-level generated sdf for all corners
* fix absolute path for mgmt_core_wrapper
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
based on feedback from tim in order to generate a lef view
with a zero origin and avoid any hacks
+ add caravel_power_routing lef
+ sync caravel_power_routing gds and mag
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
xschem-generated schematic netlist.
NOTE: None of these modifications change the function of any circuit. The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate. This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled. It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.
* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).
* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
the clocking subcircuit from inside the pad area near the "clock"
pin to under the DLL. This prevents the DLL from having its
outputs travel all the way across the chip to reach the clocking
cell and then have the multiplexed clock travel all the way back,
especially as the DLL outputs are high-speed signals (up to 150
MHz).
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
Marwan Abbas
Tim Edwards
Marwan Abbas
kareem