3 Commits

Author	SHA1	Message	Date
M0stafaRady	e94a8e0477	add test la test	2022-10-08 06:25:26 -07:00
M0stafaRady	f8c8d831d0	Add RTL for 2 debug regs used to test and located inside user_project_wrapper	2022-09-30 03:52:34 -07:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00