43ced83bd8
Correction to the mprj_bitbang testbench to run the test without running
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into issues of contention between the SPI and wishbone interfaces. The
testbench now passes, although the contention isn't handled particularly
well.
2021-10-21 10:57:20 -04:00
184f4a637c
Added the rest of the testbenches: mprj_bitbang, perf, pll, qspi, and
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storage. Not all of these pass simulation checks. Added back the
bit-bang control of the GPIO programming. Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports. There is not yet a testbench for the SRAM read-only
interface.
2021-10-19 19:05:47 -04:00
767342e183
Added a completely revised sysctrl testbench based on accessing the
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housekeeping SPI through the back-door wishbone interface. Checks
most of the SPI registers (but could do more).
2021-10-19 17:32:20 -04:00
0fa2e3bb89
Added testbenches for irq, mem, mprj_ctrl, and pass_thru (note that "mem"
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does not pass yet and still needs to be debugged).
2021-10-18 20:32:50 -04:00
2e57b5da08
Added and debugged two more testbenches, gpio_mgmt and hkspi.
2021-10-18 11:25:26 -04:00
33ca4e11ef
Additional corrections, mostly to the housekeeping module. The
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top-level simulation now passes the GPIO testbench.
2021-10-17 21:38:40 -04:00
1863a7c529
A number of small corrections.
2021-10-16 23:55:57 -04:00
842200b7ec
Changed the memory map to move the 2e and 2f wishbone domains into
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the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262... Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
2021-10-16 17:58:36 -04:00
2f74fa83ee
Reinstated the logic analyzer as a standard interface for the
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management SoC.
2021-10-16 17:42:24 -04:00
bdfa747145
First major update; current code passes syntax checks in iverilog
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and simulates, but fails testbench (not surprising at this stage).
2021-10-15 21:49:49 -04:00
332f9ec2e7
Seeding with documentation of pinout and verilog RTL (mostly unchanged
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from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
2021-10-12 16:31:42 -04:00
Tim Edwards